The present invention relates to a phase lock loop system.
There are numerous situations requiring precise phase and frequency synchronization between a local oscillatory source and an external reference signal. For example, in telephone PCM systems there is a need for synchronizing a local oscillator with the frame synchronization signals carried by the incoming transmission. That is, demodulation of the pulse code modulated signals requires an accurately timed clock synchronized with the clock at the point of origin.
For various reasons such as external noise, power surges or interruptions, or the like, the incoming reference clock signals experience interruptions which can vary from a brief fraction of a second to a second or more. Nevertheless, in order to avoid unnecessary loss of the communication signal it is essential that any receiving system have the capability of reacquiring synchronization in the shortest time possible.
In telephone communication, domestic and European PCM systems operate with different carrier frequencies. In Europe the current standard is 2.048 MHz while the American standard is 1.544 MHz, both frequencies having a common factor of 8 KHz. It is thus convenient to use the 8 KHz content of the PCM transmission as a reference signal to which the local oscillators are locked for insuring demodulation with good fidelity.
A phase lock loop is a circuit for maintaining phase coincidence between a local oscillatory source and a reference signal. The basic components of any phase lock loop are a phase detector to which the reference signal and local signal are applied, a filter for smoothing the output of the phase detector, and a controllable oscillator responsive to the filter output for providing the local signal. Both analog and digital as well as hybrid phase lock loop circuits are known. However, we are not aware of any known system that is able to acquire lock consistently in the short span of 1 second or less and, once locked, can maintain frequency and phase with interruptions of the reference signal up to at least one second with no more than 0.2 Hz deviation and 20% phase drift from the reference signal.
It is, therefore, an object of the present invention to provide a digital type phase lock loop system having the ability to quickly acquire lock upon power turn-on, to maintain such lock with close tolerance in the presence of a reference signal, and to bridge short reference signal interruptions with negligible change in local frequency and phase.